psoctools | example configs

Some example configurations for tutorial and reference purposes.
        
    openocd --verbose -c "interface kitprog; kitprog_init_acquire_psoc" -f target/psoc5lp.cfg
    telnet localhost 4444
        
        

example 0: light up the blue led (portpin 2.1) through a DSI block

        
    ;# light up the blue led on portpin 2.1 when 3.3v is applied to portpin 2.2
    ;# routes through DSI5_DSIINP into DSI5_HC and back out through DSIOUTT to the blue led
    mwb 0x40005110 0x00 96   ;# PRT1-PRT6
    mwb 0x400051C0 0x00 16   ;# PRT12_DR
    mwb 0x400051F0 0x00 16   ;# PRT15_DR
    mwb 0x40010000 0x00 4096 ;# UDB Bank 0
    mwb 0x40011400 0x00 2048 ;# UDB Bank 1
    mwb 0x40014000 0x00 2560 ;# DSI0
    mwb 0x40014C00 0x00 512  ;# DSI12
    mwb 0x40015000 0x00 32   ;# MDCLK_EN
    mwb 0x40005210 0x02 1    ;# PRT2_OUT_SEL0
    mwb 0x40005211 0x02 1    ;# PRT2_OUT_SEL1
    mwb 0x400145C0 0x02 1    ;# DSI5_DSIINP0
    mwb 0x400145D6 0x04 1    ;# DSI5_DSIOUTT1
    mwb 0x40005122 0x06 1    ;# PRT2_DM0
    mwb 0x40005123 0x06 1    ;# PRT2_DM1
    mwb 0x40005124 0x00 1    ;# PRT2_DM2
    mwb 0x40005125 0x00 1    ;# PRT2_SLW
    mwb 0x40005126 0x02 1    ;# PRT2_BYP
    mwb 0x40005127 0x00 1    ;# PRT2_BIE
    mwb 0x40005128 0x00 1    ;# PRT2_INP_DIS
    mwb 0x40005129 0x00 1    ;# PRT2_CTL
    mwb 0x40015003 0x02 1    ;# BCTL0_BANK_CTL
    mwb 0x40015013 0x02 1    ;# BCTL1_BANK_CTL

    mwb 0x40005012 0x0D 1    ;# PRT2_PC2 -- light it up!
    sleep 3000
    mwb 0x40005012 0x0C 1    ;# PRT2_PC2 -- turn it off
    sleep 3000
    mwb 0x40005012 0x0D 1    ;# PRT2_PC2 -- light it up!
        
        

example 1: traverse two DSI blocks horizontally

Effectively all that needed to be added from the previous example was DSI5_HS8. The drive mode settings were changed to configure portpin 6.2 as input instead of portpin 2.2. DSIINP is now set up for DSI4 rather than DSI5 because port 6 is associated with DSI4.
        
    ;# light up the blue led on portpin 2.1 when 3.3v is applied to portpin 6.2
    mwb 0x40005110 0x00 96   ;# PRT1-PRT6
    mwb 0x400051C0 0x00 16   ;# PRT12_DR
    mwb 0x400051F0 0x00 16   ;# PRT15_DR
    mwb 0x40010000 0x00 4096 ;# UDB Bank 0
    mwb 0x40011400 0x00 2048 ;# UDB Bank 1
    mwb 0x40014000 0x00 2560 ;# DSI0
    mwb 0x40014C00 0x00 512  ;# DSI12
    mwb 0x40015000 0x00 32   ;# MDCLK_EN
    mwb 0x40005210 0x02 1    ;# PRT2_OUT_SEL0
    mwb 0x40005211 0x02 1    ;# PRT2_OUT_SEL1
    mwb 0x400144C0 0x02 1    ;# DSI4_DSIINP0
    mwb 0x400145D6 0x04 1    ;# DSI5_DSIOUTT1

    mwb 0x40014590 0x04 1    ;# DSI5_HS8

    ;# configure portpins 6.2 (input) and 2.1 (output to blue led)
    mwb 0x40005162 0x04 1    ;# PRT6_DM0
    mwb 0x40005163 0x04 1    ;# PRT6_DM1
    mwb 0x40005164 0x00 1    ;# PRT6_DM2
    mwb 0x40005165 0x00 1    ;# PRT6_SLW
    mwb 0x40005166 0x00 1    ;# PRT6_BYP
    mwb 0x40005167 0x00 1    ;# PRT6_BIE
    mwb 0x40005168 0x00 1    ;# PRT6_INP_DIS
    mwb 0x40005169 0x00 1    ;# PRT6_CTL
    mwb 0x40005122 0x02 1    ;# PRT2_DM0
    mwb 0x40005123 0x02 1    ;# PRT2_DM1
    mwb 0x40005124 0x00 1    ;# PRT2_DM2
    mwb 0x40005125 0x00 1    ;# PRT2_SLW
    mwb 0x40005126 0x02 1    ;# PRT2_BYP
    mwb 0x40005127 0x00 1    ;# PRT2_BIE
    mwb 0x40005128 0x00 1    ;# PRT2_INP_DIS
    mwb 0x40005129 0x00 1    ;# PRT2_CTL
    mwb 0x40015003 0x02 1    ;# BCTL0_BANK_CTL
    mwb 0x40015013 0x02 1    ;# BCTL1_BANK_CTL
    
    ;# apply 3.3v to portpin 6.2 or set it through software
    mwb 0x40005160 0x04 1    ;# PRT6_DR -- light it up!
    sleep 3000                                                     
    mwb 0x40005160 0x00 1    ;# PRT6_DR -- turn it off 
    sleep 3000                                                     
    mwb 0x40005160 0x04 1    ;# PRT6_DR -- light it up!

        
        

example 2: traverse many DSI blocks horizontally

        
    ;# light up the blue led on portpin 2.1 when 3.3v is applied to portpin 5.2
    ;# this example traverses many DSI blocks with the HS (Horizontal Segment) registers
    mwb 0x40005110 0x00 96   ;# PRT1-PRT6
    mwb 0x400051C0 0x00 16   ;# PRT12_DR
    mwb 0x400051F0 0x00 16   ;# PRT15_DR
    mwb 0x40010000 0x00 4096 ;# UDB Bank 0
    mwb 0x40011400 0x00 2048 ;# UDB Bank 1
    mwb 0x40014000 0x00 2560 ;# DSI0
    mwb 0x40014C00 0x00 512  ;# DSI12
    mwb 0x40015000 0x00 32   ;# MDCLK_EN
    mwb 0x40005210 0x02 1    ;# PRT2_OUT_SEL0
    mwb 0x40005211 0x02 1    ;# PRT2_OUT_SEL1
    
    mwb 0x40014DC0 0x02 1    ;# DSI13_DSIINP0
    
    ;# traverse many DSI blocks horizontally
    mwb 0x40014694 0x40 1    ;# DSI6_HS8
    mwb 0x40014794 0x40 1    ;# DSI7_HS8
    mwb 0x40014C94 0x40 1    ;# DSI12_HS8
    mwb 0x40014D94 0x40 1    ;# DSI13_HS8
    
    mwb 0x400145D6 0x04 1    ;# DSI5_DSIOUTT1
   
    mwb 0x40005122 0x02 1    ;# PRT2_DM0
    mwb 0x40005123 0x02 1    ;# PRT2_DM1
    mwb 0x40005124 0x00 1    ;# PRT2_DM2
    mwb 0x40005125 0x00 1    ;# PRT2_SLW
    mwb 0x40005126 0x02 1    ;# PRT2_BYP
    mwb 0x40005127 0x00 1    ;# PRT2_BIE
    mwb 0x40005128 0x00 1    ;# PRT2_INP_DIS
    mwb 0x40005129 0x00 1    ;# PRT2_CTL
    
    mwb 0x40005152 0x04 1    ;# PRT5_DM0
    mwb 0x40005153 0x04 1    ;# PRT5_DM1
    mwb 0x40005154 0x00 1    ;# PRT5_DM2
    mwb 0x40005155 0x00 1    ;# PRT5_SLW
    mwb 0x40005156 0x00 1    ;# PRT5_BYP
    mwb 0x40005157 0x00 1    ;# PRT5_BIE
    mwb 0x40005158 0x00 1    ;# PRT5_INP_DIS
    mwb 0x40005159 0x00 1    ;# PRT5_CTL
    
    mwb 0x40015003 0x02 1    ;# BCTL0_BANK_CTL
    mwb 0x40015013 0x02 1    ;# BCTL1_BANK_CTL
     
    ;# apply 3.3v to portpin 5.2 or set it through software
    mwb 0x40005150 0x04 1    ;# PRT5_DR -- light it up!
    sleep 3000
    mwb 0x40005150 0x00 1    ;# Turn it off
    sleep 3000
    mwb 0x40005150 0x04 1    ;# PRT5_DR -- light it up!
       
        

example 3: OR 1.3, 1.2 -> 2.1 with DSI routing only

I just got Boolean AND and Boolean OR to work in the DSI without relying on PLD's. Although, there is improvement to be made with responsiveness. I improved the responsiveness of the Boolean OR but I still need to improve the Boolean AND.

UPDATE

It looks like the problem is with openocd. The responsiveness is significantly better when I provide inputs to actual gpios of the CY8CKIT-059. Here's some examples with input routed from 1.3 and 1.2 which are broken out on the board.
        
    ;# Boolean OR from portpins 1.3 and 1.2 to the blue led at 2.1
    mwb 0x40005110 0x00 96   ;# PRT1-PRT6
    mwb 0x400051C0 0x00 16   ;# PRT12_DR
    mwb 0x400051F0 0x00 16   ;# PRT15_DR
    mwb 0x40010000 0x00 4096 ;# UDB Bank 0
    mwb 0x40011400 0x00 2048 ;# UDB Bank 1
    mwb 0x40014000 0x00 2560 ;# DSI0
    mwb 0x40014C00 0x00 512  ;# DSI12
    mwb 0x40015000 0x00 32   ;# MDCLK_EN
    mwb 0x40005210 0x02      ;# PRT2_OUT_SEL0
    mwb 0x40005211 0x02      ;# PRT2_OUT_SEL1
    
    ;# these two switches are on different rows:
    mwb 0x40014C00 0x80      ;# DSI12_HC0
    mwb 0x40014C04 0x80      ;# DSI12_HC4

    mwb 0x40014CC0 0x03      ;# DSI12_DSIINP0
    
    mwb 0x40014C94 0x40      ;# DSI12_HS4
    mwb 0x40014794 0x40      ;# DSI7_HS4
    mwb 0x40014694 0x40      ;# DSI6_HS4
   
    mwb 0x400145D6 0x04      ;# DSI5_DSIOUTT1
    
    mwb 0x40005122 0x02      ;# PRT2_DM0
    mwb 0x40005123 0x02      ;# PRT2_DM1
    mwb 0x40005124 0x00      ;# PRT2_DM2
    mwb 0x40005125 0x00      ;# PRT2_SLW
    mwb 0x40005126 0x02      ;# PRT2_BYP
    mwb 0x40005127 0x00      ;# PRT2_BIE
    mwb 0x40005128 0x00      ;# PRT2_INP_DIS
    mwb 0x40005129 0x00      ;# PRT2_CTL
    
    mwb 0x40005112 0x0C      ;# PRT1_DM0
    mwb 0x40005113 0x0C      ;# PRT1_DM1
    mwb 0x40005114 0x00      ;# PRT1_DM2
    mwb 0x40005115 0x00      ;# PRT1_SLW
    mwb 0x40005116 0x00      ;# PRT1_BYP
    mwb 0x40005117 0x00      ;# PRT1_BIE
    mwb 0x40005118 0x00      ;# PRT1_INP_DIS
    mwb 0x40005119 0x00      ;# PRT1_CTL
    
    mwb 0x40015003 0x02      ;# BCTL0_BANK_CTL
    mwb 0x40015013 0x02      ;# BCTL1_BANK_CTL

    ;# mwb 0x40005110 0x0C      ;# 1 1
    ;# mdb 0x40005121           ;# 1

    ;# mwb 0x40005110 0x08      ;# 1 0
    ;# mdb 0x40005121           ;# 1

    ;# mwb 0x40005110 0x04      ;# 0 1
    ;# mdb 0x40005121           ;# 1

    ;# mwb 0x40005110 0x00      ;# 0 0
    ;# sleep 1000               ;# OpenOCD or SWD needs this delay, the hardware doesn't seem to need it.
    ;# mdb 0x40005121           ;# 0       
         
        
Try it with physical pins or through openocd:
        
    openocd --verbose -c "interface kitprog; kitprog_init_acquire_psoc" -f target/psoc5lp.cfg
    telnet localhost 4444
    > source boolean-or.cfg
    0x40005121 02                                              .               
    0x40005121 02                                              .               
    0x40005121 02                                              .               
    0x40005121 00                                              .               
       
        

example 4: AND 1.3, 1.2 -> 2.1 with DSI routing only

        
    ;# Boolean AND from portpins 1.3 and 1.2 to the blue led at 2.1
    mwb 0x40005110 0x00 96   ;# PRT1-PRT6
    mwb 0x400051C0 0x00 16   ;# PRT12_DR
    mwb 0x400051F0 0x00 16   ;# PRT15_DR
    mwb 0x40010000 0x00 4096 ;# UDB Bank 0
    mwb 0x40011400 0x00 2048 ;# UDB Bank 1
    mwb 0x40014000 0x00 2560 ;# DSI0
    mwb 0x40014C00 0x00 512  ;# DSI12
    mwb 0x40015000 0x00 32   ;# MDCLK_EN
    mwb 0x40005210 0x02      ;# PRT2_OUT_SEL0
    mwb 0x40005211 0x02      ;# PRT2_OUT_SEL1
    
    mwb 0x40014CC0 0x03      ;# DSI12_DSIINP0

    ;# these two switches are on the same row:
    mwb 0x40014C00 0x40      ;# DSI12_HC0
    mwb 0x40014C04 0x40      ;# DSI12_HC4
  
    mwb 0x40014C94 0x40      ;# DSI12_HS4
    mwb 0x40014794 0x40      ;# DSI7_HS4
    mwb 0x40014694 0x40      ;# DSI6_HS4
   
    mwb 0x400145D6 0x04      ;# DSI5_DSIOUTT1
    
    mwb 0x40005122 0x02      ;# PRT2_DM0
    mwb 0x40005123 0x02      ;# PRT2_DM1
    mwb 0x40005124 0x00      ;# PRT2_DM2
    mwb 0x40005125 0x00      ;# PRT2_SLW
    mwb 0x40005126 0x02      ;# PRT2_BYP
    mwb 0x40005127 0x00      ;# PRT2_BIE
    mwb 0x40005128 0x00      ;# PRT2_INP_DIS
    mwb 0x40005129 0x00      ;# PRT2_CTL
    
    mwb 0x40005112 0x0C      ;# PRT1_DM0
    mwb 0x40005113 0x0C      ;# PRT1_DM1
    mwb 0x40005114 0x00      ;# PRT1_DM2
    mwb 0x40005115 0x00      ;# PRT1_SLW
    mwb 0x40005116 0x00      ;# PRT1_BYP
    mwb 0x40005117 0x00      ;# PRT1_BIE
    mwb 0x40005118 0x00      ;# PRT1_INP_DIS
    mwb 0x40005119 0x00      ;# PRT1_CTL
    
    mwb 0x40015003 0x02      ;# BCTL0_BANK_CTL
    mwb 0x40015013 0x02      ;# BCTL1_BANK_CTL

    ;# mwb 0x40005110 0x0C      ;# 1 1
    ;# sleep 100                ;# OpenOCD or SWD needs this delay, the hardware doesn't seem to need it.
    ;# mdb 0x40005121           ;# 1

    ;# mwb 0x40005110 0x08      ;# 1 0
    ;# sleep 100                ;# OpenOCD or SWD needs this delay, the hardware doesn't seem to need it.
    ;# mdb 0x40005121           ;# 0

    ;# mwb 0x40005110 0x04      ;# 0 1
    ;# sleep 100                ;# OpenOCD or SWD needs this delay, the hardware doesn't seem to need it.
    ;# mdb 0x40005121           ;# 0

    ;# mwb 0x40005110 0x00      ;# 0 0
    ;# sleep 100                ;# OpenOCD or SWD needs this delay, the hardware doesn't seem to need it.
    ;# mdb 0x40005121           ;# 0
        
        
Try it with physical pins or through openocd:
        
    openocd --verbose -c "interface kitprog; kitprog_init_acquire_psoc" -f target/psoc5lp.cfg
    telnet localhost 4444
    > source boolean-and.cfg
    0x40005121 02                                              .               
    0x40005121 00                                              .               
    0x40005121 00                                              .               
    0x40005121 00                                              .               
    > 
       
        

example 5: XOR using status and control block for io

Strangely this example works when run from the arm using mecrisp-stellaris forth for psoc5lp, but not from swd+openocd+telnet.
        
    ;# xor using status and control blocks for io
    mwb 0x40010000 0x00 0x1000 ;# UDB Bank 0
    mwb 0x40011400 0x00 0x800  ;# UDB Bank 1
    mwb 0x40014000 0x00 0xA00  ;# DSI0
    mwb 0x40014C00 0x00 0x200  ;# DSI12
    mwb 0x40015000 0x00 0x20   ;# MDCLK_EN
    
    mwb 0x40015003 0x00 ;# BCTL0_BANK_CTL
    mwb 0x40015013 0x00 ;# BCTL1_BANK_CTL
    
    mwb 0x40010AA4 0x01 ;# B0_P5_U1_PLD0_IT9C
    mwb 0x40010AA6 0x02 ;# B0_P5_U1_PLD0_IT9T
    mwb 0x40010AAC 0x02 ;# B0_P5_U1_PLD0_IT11C
    mwb 0x40010AAE 0x01 ;# B0_P5_U1_PLD0_IT11T
    mwb 0x40010AB0 0x03 ;# B0_P5_U1_PLD0_ORT0
    mwb 0x40010ABE 0x01 ;# B0_P5_U1_PLD0_MC_CFG_BYPASS
    mwb 0x40010AD8 0x04 ;# B0_P5_U1_CFG24
    mwb 0x40010ADB 0x04 ;# B0_P5_U1_CFG27
    mwb 0x40010ADF 0x01 ;# B0_P5_U1_CFG31
    mwb 0x40010B15 0x40 ;# B0_P5_ROUTE_HC21
    mwb 0x40010B17 0x04 ;# B0_P5_ROUTE_HC23
    mwb 0x40010B1E 0x80 ;# B0_P5_ROUTE_HC30
    mwb 0x40010B5E 0x80 ;# B0_P5_ROUTE_HC94
    mwb 0x40010B6D 0x40 ;# B0_P5_ROUTE_HC109
    mwb 0x40010B6F 0x04 ;# B0_P5_ROUTE_HC111
    mwb 0x40010BC4 0xA0 ;# B0_P5_ROUTE_PLD0IN2
    mwb 0x40010BD6 0x10 ;# B0_P5_ROUTE_SCIN
    
    mwb 0x40015003 0x02 ;# BCTL0_BANK_CTL
    mwb 0x40015013 0x02 ;# BCTL1_BANK_CTL
    
    ;# write inputs to B0_UDB11_CTL register
    ;# ...and read result from B0_UDB11_ST
    mwb 0x4000647B 0x00
    mdb 0x400068D6
    
    mwb 0x4000647B 0x01
    mdb 0x400068D6
    
    mwb 0x4000647B 0x10
    mdb 0x400068D6
    
    mwb 0x4000647B 0x11
    mdb 0x400068D6